The present disclosure generally relates to scaling of integrated circuits and, in particular, to lowering contact resistance associated with integrated circuit transistors having device dimensions below 20 nm.
As integrated circuit transistors become smaller, making electrical contact to the transistor terminals becomes more and more challenging. As the contact area shrinks, the associated contact resistance increases according to the relationship R=ρ I/A, wherein A is the contact surface area at the point of contact through which current flows, I is the height of the contact in the direction of current flow, and p is the resistivity of the contact metal. Increases in contact resistance significantly degrade overall device performance. Thus, it is important to address and compensate for the increased contact resistance that occurs with each new technology generation by making changes in the transistor design, the contact design, or the transistor fabrication process.
Another problem that occurs when forming contacts to transistor source and drain regions is that formation of the contact openings tends to erode underlying dielectric materials at a fast rate. Such dielectric materials may include sidewall spacers or a cap that protects the gate structure during formation of contacts to the source and drain. In the past, such dielectric materials covering the gate electrode were simply made thicker to compensate for the erosion. However, smaller transistor dimensions now prevent further thickening the dielectric material covering the gate electrode.